Positive Bias Temperature Instability Research Articles

Assessment of BTI‐induced deterioration in vacuum based undoped structure

AbstractIn this paper, an assessment of bias temperature instability (BTI) in based dual gate dopingless JLFET (HKV‐DLJLFET) is carried out at 15 nm technology node. For this, the gate dielectric of HKV‐DGDLJLFET is made of asymmetric combination of and vacuum dielectrics near the source/drain (S/D) side, which significantly minimizes the leakage current and enhances the reliability. Our simulation study have shown that the n‐type HKV‐DGDLJLFET exhibits 2.28 and 2.45 times less deterioration in drain current and transconductance respectively, than n‐type HKV‐DGJLFET due to positive BTI (PBTI) for 2000 seconds at . Further, we have found that n‐type HKV‐DGDLJLFET has less deterioration in and due to BTI stress for different time spans. Hence, adding vacuum dielectric to the drain side lowers the BTI stress at high temperatures and makes it last longer.

Hot-Carrier Damage in N-Channel EDMOS Used in Single Photon Avalanche Diode Cell through Quasi-Static Modeling.

A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The stressing gate-voltage (VGS) dependence is compared to hot-hole (HH) injection, positive bias temperature (PBT) instability and off-mode (VGS = 0). The goal was to check an accurate device lifetime extraction using accelerated DC to AC stressing by applying the quasi-static (QS) lifetime technique. N-EDMOS device is devoted to 3D bonding with CMOS imagers obtained by an optimized process with an effective gate-length Leff = 0.25 µm and a SiO2 gate-oxide thickness Tox = 5 nm. The operating frequency is 10 MHz at maximum supply voltage VDDmax = 5.5 V. TCAD simulations are used to determine the real voltage and timing configurations for the device in a mixed structure of the SPAD cell. AC device lifetime is obtained using worst-case DC accelerating degradation, which is transferred by QS technique to the AC waveforms applied to N-EDMOS device. This allows us to accurately obtain the AC device lifetime as a function of the delay and load for a fixed pulse shape. It shows the predominance of the high energy hot-carriers involved in the first substrate current peak during transients.

Aging-Aware Critical Path Selection via Graph Attention Networks

In advanced technology nodes, aging effects like negative and positive bias temperature instability (NBTI and PBTI) become increasingly significant, making timing closure and optimization more challenging. Unfortunately, conventional critical path selection tools used in reliability-aware design flow cannot accurately identify critical paths under different aging conditions. To address this issue, we propose an aging-aware critical path selection flow comprising two parts: critical cell detection and path criticality computation. We employ graph-attention networks (GATs) to predict the critical cells in the aged circuits, and a path criticality computation algorithm that takes into account circuit-level and transistor-level parameters to generate path criticality rank lists. Our experimental results demonstrate that our GAT model outperforms classical machine learning models in detecting critical cells. Additionally, compared with the commercial tool, our aging-aware flow achieves an average accuracy of 99.52%, 98.69%, and 97.20% for top-10%, top-5%, and top-1% path sets respectively, in five industrial designs subjected to different aging conditions and workloads.

Threshold voltage instability in SiO2-gate semi-vertical GaN trench MOSFETs grown on silicon substrate

We analyze the threshold voltage stability under positive gate stress in semi-vertical GaN trench MOSFETs with silicon oxide gate insulator. The experimental results, obtained by a fast setup capable of recording the threshold voltage transient with stress time as low as 10 μs, indicate that positive gate voltage induces a trapping of electrons in oxide border traps. In addition, experimental data obtained at different temperature and recovery bias conditions suggest that trapping proceeds through tunneling, from the inversion channel in the p-GaN layer to the traps. Finally, we developed a mathematical framework to model such tunneling process that conceptually explains the origin of the strongly stretched trapping transients and the results were compared with some relevant references on positive bias temperature instability in Si and GaN based devices.

DC to AC analysis of HC vs. BTI damage in N-EDMOS used in single photon avalanche diode cell

N-channel Extended Drain Metal Oxide Semiconductor (EDMOS) device is analysed through its sensitivity to Hot-Carrier (HC), hot hole (HH) injections and Positive Bias Temperature (PBT) instability degradation using accelerated DC to AC lifetime technique. EDMOS device is optimized for an effective gate-length Leff = 0.25 μm, with a gate-oxide thickness Tox = 5 nm operating at a frequency of 3 MHz at nominal supply voltage VDD = 5 V. The device is used in a mixed structure dedicated to 3D integration of Single Photon Avalanche Diode (SPAD). We show that HC reliability of EDMOS transistor can be obtained using worst-case DC accelerating degradation at high temperature transferred to the real AC waveforms applied to N-channel device placed into the SPAD cell. This allows to deduce the AC device lifetime obtained from DC stressing using a quasi-static approach considering the dominant degradation mechanism at condition of maximum gate-voltage VGSmax. This is explained by the optimized structure in Tox, VDD and lateral isolation where PBT, Off mode and recovery effects have limited impacts during switching operation of the N-EDMOS device used in SPAD circuit environment.

Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs.

We study how nitridation, applied to SiON gate layers, impacts the reliability of planar metal-oxide-semiconductor field effect transistors (MOSFETs) subjected to negative and positive bias temperature instability (N/PBTI) as well as hard breakdown (HBD) characteristics of these devices. Experimental data demonstrate that p-channel transistors with SiON layers characterized by a higher nitrogen concentration have poorer NBTI reliability compared to their counterparts with a lower nitrogen content, while PBTI in n-channel devices is negligibly weak in all samples independently of the nitrogen concentration. The Weibull distribution of HBD fields extracted from experimental data in devices with a higher N density are shifted towards lower values with respect to that measured in MOSFETs, and SiON films have a lower nitrogen concentration. Based on these findings, we conclude that a higher nitrogen concentration results in the aggravation of BTI robustness and HBD characteristics.

Role of interface/border traps on the threshold voltage instability of SiC power transistors

In this paper the role of interface/border defects on the threshold voltage drift (ΔVTH) of SiC power MOSFETs has been investigated by means of slow and fast positive bias temperature instability (PBTI), hysteresis and conductance tests. Results have shown an opposite temperature (T) dependency based on the level of the applied gate bias (VG) and on the adopted stress technique. With VG > 30 V and a slow-PBTI procedure, the creation of new oxide defects and/or the charge trapping in deep states occurs, showing a positive T-dependency. On the contrary, with a lower VG and a fast-PBTI test, the ΔVTH shows a negative T-dependency, associated to dominant role of pre-existing interface and/or border traps.

1/f noise of short-channel indium tin oxide transistors under stress

In this work, we investigate the reliability and stability of short-channel indium tin oxide (ITO) field-effect transistors through 1/f noise characterization at elevated temperature with positive bias temperature instability (PBTI). The 1/f noise behavior of a short-channel 60-nm-long channel ITO transistor can be described by the carrier number fluctuation model, suggesting that carrier trapping and de-trapping by trap states within the 5 nm thin high-κ HfLaO dielectric are the dominant mechanisms affecting 1/f noise. Small positive threshold voltage shifts of 0.042 and 0.057 V after PBTI measurements of 3000 s at 25 and 85 °C have been obtained, respectively. The higher gate leakage current at elevated temperature leads to an earlier breakdown in the time-dependent dielectric breakdown measurement. Furthermore, 1/f noise after PBTI has also been carried out at elevated temperature, and the degradations after stress can also be attributed to the stress induced traps inside the gate dielectric.

Analysis of Hump Effect Induced by Positive Bias Temperature Instability in the Local Oxidation of Silicon n-MOSFETs

In this study, the degradation of the subthreshold swing (S.S.) and the hump effect are observed in the local oxidation of silicon (LOCOS) metal-oxide-semiconductor field-effect transistors (MOSFETs) under short-and long-term positive bias temperature instability tests, respectively. S.S. collapse is considered to be caused by anode hot-hole injection, and the hump effect occurs because the geometric structure from LOCOS isolation forms parasitic transistors on both sides of the channel, which can be verified by a Silvaco Technology computer-aided design (TCAD) simulation. In addition, the body effect measurement method is proposed to elucidate the mechanism of the hump effect for further confirmation of hump formation.

A Comparative Study between Negative & Positive Bias Temperature Instability of Commercial nano-MOSFETs Using Voltage Step Stress Technique

Bias temperature instability (BTI) has been one of the most common and also severe aging mechanisms in MOSFETs. In this work, a comparative study between NBTI and PBTI of commercial nano-MOSFETs has been conducted using the voltage step stress (VSS) technique, which is implemented by applying multiple constant voltage stress (CVS) continuously on a single device. Aging parameters are extracted for both NBTI and PBTI from a single device using the VSS technique, and the lifetime under room temperature is predicted. This work is of potential use for BTI investigation of commercial nano-MOSFETs in terms of both test efficiency and affordability.

Ab initio investigations in amorphous silicon dioxide: Proposing a multi-state defect model for electron and hole capture

Experiments as well as theoretical calculations indicate that point defects in the amorphous SiO2 layer of electronic devices as well as in optical fibers are responsible for numerous stability and reliability phenomena, including noise, hysteresis, bias temperature instabilities and decreasing transmission efficiency. In addition to the well-known oxygen vacancy, hydrogen related defects such as the hydrogen bridge and the hydroxyl-E′ center have gained a considerable amount of attention in the recent past, as they are suspected to negatively influence the device performance by capturing charge carriers from e.g. both Si and SiC substrates in field effect transistors. Here, we present a thorough ab initio study of these oxide defects and develop a unified description of electron and hole capture processes in a single multi-state model, supported by a comprehensive analysis of various defect parameters like relaxation energies, charge transition levels, (meta-)stability and transition barriers. We show that a single oxide defect can have two different trap levels for both electron and hole capturing processes, which might be the cause of anomalous device degradation phenomena. Based on its low formation energy compared to other defect types, we find that the hydroxyl-E′ center is the most promising defect candidate to explain charge capture processes in Si/SiO2 systems. Furthermore, we argue that the reduced effect of positive bias temperature instability (PBTI) observed in MOS devices compared to its negative counterpart (NBTI) can be explained by the locations of the hydroxyl-E′ centers charge transition levels.

(Digital Presentation) Negative Bias Illumination Stress on a-Igzo TFT with a Top Barrier

The double-layer a-IGZO thin film transistors (DL-TFTs) using a quantum well channel and a top barrier can improve not only the electrical properties and the positive bias temperature instability as compared to the single-layer TFT (SL-TFTs) [1][2] but also the negative bias illumination stress (NBIS). In this work, DL-TFTs have less negative VT shifts than that of SL-TFTs under NBIS. Moreover, the negative VT shift of DL-TFTs decreases with increasing top barrier thickness due to the energy barrier formed by the valence band discontinuity at the interface between the channel layer and the top barrier. Experimental Process: The 100 nm Mo/Al layers were first deposited on a glass substrate and patterned to form the bottom gate (BG) metal, followed by the deposition of 320 nm thick SiNx/SiOx gate insulator (GI) using plasma-enhanced chemical vapor deposition (PECVD). For the active layer of SL-TFT, 15 nm a-IGZO with high indium content was deposited to form a high mobility channel (HM-IGZO) using radio frequency magnetron sputtering with Ar plasma. As for the DL-TFTs, an extra standard a-IGZO (STD-IGZO, the atomic composition of the target is In2O3:Ga2O3:ZnO=1:1:2 mol%) was deposited as a top barrier. Two different top barrier thicknesses were deposited (10 nm and 30 nm) to investigate the thickness effect on the NBIS. The active layer was then patterned by photolithography. A 260 nm Ti was deposited and patterned by photolithography and reactive ion etch (RIE) as the S/D metal, followed by SiOx/SiNx top gate insulator deposition and the transparent indium tin oxide (ITO) top gate (TG) metal formation. To conduct the NBIS test, -30 V and 0 V were applied to the bottom gate and the top gate, respectively, and a light source with a wavelength of 365 nm was used as the illumination stress. Additional 100 nm films of HM and STD IGZO were deposited to investigate the band alignment. The bandgap (Eg), valence band offsets (EF-EV, where EF is the Fermi level and EV is the valence band edge), and work function can be extracted by Tauc method, X-Ray photoelectron spectroscopy (XPS), and Kelvin probe force microscopy (KPFM), respectively, to obtain the band alignment of the HM (channel layer) and the STD (top barrier) IGZO [3]. Results and Discussions: The evolution of VT shifts under NBIS are shown in Fig. 1. DL-TFTs have less VT shift than that of SL-TFT. Since the energy of the photon (3.4 eV) is larger than the bandgap of the a-IGZO (~3 eV), electron-hole pairs are generated by the light source. Since a negative voltage is applied to the BG, the generated holes are trapped into the BG GI, resulting in the negative VT shift. In DL-TFTs, the holes generated in the top barrier cannot be trapped into the BG GI due to the energy barrier formed by the valence band discontinuity. With the band alignment analysis [1], the valence band discontinuity is found to be 0.39 eV, which is high enough to stop the holes generated in the top barrier from trapping into the BG GI. The electrons generated in the top barrier can still be trapped into the TG GI, compensating the negative VT shift (Fig. 2(a)), resulting in a smaller VT shift in DL-TFTs than that of SL-TFTs. Reportedly, the VT shift increases with increasing a-IGZO thickness in SL-TFTs [4]. However, the VT shift decreases with increasing top barrier thickness in DL-TFTs (Fig. 1). Although the generated electron-hole pairs in the top barrier increase with increasing top barrier thickness, the additional holes cannot be trapped into the BG GI due to the valence band discontinuity, while the additional electrons can easily be trapped into the TG GI, leading to more VT shift compensation and thus less negative VT shift in the DL-TFT (Fig. 2(b)). Conclusion: The DL-TFTs have less VT shift under NBIS as compared to SL-TFTs. The NBIS can be further improved by increasing the top barrier thickness. Acknowledgment: This work was supported in part by the Ministry of Science and Technology, Taiwan, under Grant MOST 110-2218-E-A49-013-MBK, Grant MOST 110-2218-E-002-030, and Grant MOST 110-2622-8-002-014, and in part by the Ministry of Education, Taiwan, under Grant NTU-CC-110L892601. Reference: [1] J.-C. Chiu et al., J-EDS (2021) [2] J.-C. Chiu et al., IEDMS (2021) [3] A.-H. Tai et al., TED (2019) [4] M. M. Billah et al., EDL (2016) Figure 1

Positive-Bias-Temperature-Instability Induced Random-Trap-Fluctuation Enhanced Physical Unclonable Functions on 14-nm nFinFETs

We report one sort of weak physical unclonable functions (PUFs) composed of 14-nm nFinFETs with entropy of the random-trap-fluctuation (RTF). After the positive-bias-temperature-instability (PBTI) stress at high temperatures (85 °C ~ 150 °C), the generation of abundant random traps at the interface of gate-dielectric layers and channel efficiently improves cryptographic parameters of nFinFET-PUFs. Results show that bit-error-rates of the MOSAIC plots reduce to 1.4%; average values/standard-deviation of the inter- and intra- Hamming-distance reach 50.28%/1.7% and 0.38%/0.42%, respectively. This work provides an implacable technique to boost characteristics of weak PUFs through combinations of device-reliability and cryptography.

Gate-Bias Induced Threshold Voltage (V TH) Instability in P-N Junction/AlGaN/GaN HEMT

In this work, we studied the threshold voltage ( <formula> <tex>$V_{TH}$</tex> </formula> ) instability in E-mode p-n junction (PNJ)/AlGaN/GaN high-electron-mobility transistor (HEMT) using pulsed-I/V measurement and positive bias temperature instability (PBTI) test. <formula> <tex>$V_{TH}$</tex> </formula> shifts positively under forward gate bias, which is ascribed to electron trapping in the gate-stack region. Benefiting from the special p-GaN/n-GaN junction, reduced electric field suppresses electron trapping in the PNJ gate, resulting in more stable <formula> <tex>$V_{TH}$</tex> </formula> compared with the conventional Schottky-type p-GaN gate. Specifically, less positive threshold voltage shift ( <formula> <tex>$V_{TH}$</tex> </formula> ) is observed under higher temperatures, or after being stressed for a prolonged period with gate bias exceeding 6 V. The decrease in positive <formula> <tex>$V_{TH}$</tex> </formula> results from enhanced hole injection and especially hole trapping in the p-GaN/n-GaN interdiffusion region, which compensates for electron trapping and reduces positive <formula> <tex>$V_{TH}$</tex> </formula> .

Threshold-voltage bias-instability in SiC MOSFETs: effects of stress temperature and level on oxide charge buildup and recovery

In this study we performed slow and fast bias temperature instability (BTI) measurements on n-channel silicon carbide (SiC) metal-oxide-SiC field effect transistors. Threshold voltage (V th) shifts as well as recovery observed during and after stress applied at different temperatures and stress levels were used to understand the dynamics of charge trapping/capture and detrapping/emission at gate oxide defects. It is deduced from the results that no new defects are created by the stress at the levels used in this study and V th shifts are due to the injected electron capture and trapping at existing oxide border traps. Positive gate-voltage BTI induced V th shift is observed to follow a power law on stress time with an exponent, n, dependent on stress temperature and level, such that 0.03 ⩽ n ⩽ 0.09. Electron emission and/or defect interactions are found to proceed with a low activation energy of the order of 0.01 eV and are suggested to be responsible for oxide charge reduction and, consequently, V th recovery.

Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been produced by several vendors for commercial applications. SiC-MOSFET reliability was assessed using bias-temperature instability (BTI) and time-dependent dielectric breakdown (TDDB) characteristics. Here, we compared two planar SiC-MOSFET samples (A and B) from different vendors. The samples exhibited significantly different positive and negative BTI, time-dependent gate-current, TDDB lifetime statistics, and temperature dependence. These differences suggest NO (nitric oxide)-annealing variations.

Bias Temperature Instability of MOSFETs: Physical Processes, Models, and Prediction

CMOS technology dominates the semiconductor industry, and the reliability of MOSFETs is a key issue. To optimize chip design, trade-offs between reliability, speed, power consumption, and cost must be carried out. This requires modeling and prediction of device instability, and a major source of instability is device aging, where defects gradually build up and eventually cause malfunction of circuits. This paper first gives an overview of the major aging processes and discusses their relative importance as CMOS technology developed. Attentions are then focused on the negative and positive bias temperature instabilities (NBTI and PBTI), mainly based on the early works of the authors. The aim is to present the As-grown-Generation (AG) model, which can be used not only to fit the test data but also to predict long-term BTI at low biases. The model is based on an in-depth understanding of the different types of defects and the experimental separation of their contributions to BTI. The new measurement techniques developed to enable this separation are reviewed. The physical processes responsible for BTI are explored, and the reasons for the failure of the early models in predicting BTI are discussed.

Anomalous PBTI Effects in N-Type Super Junction under High Gate Voltage Stress

In this work, an anomalous thick oxide-degradation phenomenon in n-type 650-V class super-junction VDMOS transistors is investigated. An unexpected threshold voltage (Vt) decrease was observed with high positive bias temperature instability stress, and the saturation current (IDsat) increases with the stress time. Repeatable and reproducible behaviors have been achieved from multiple devices under test. Based on simulation and experimental results, it is found that the high-energy electrons (caused by high positive gate voltage) in the n-type region at the bottom of the gate oxide layer (top of the N-pillar) are injected into the gate oxide. The high-energy electrons generate electron-hole pairs during the transport to the anode, leaving holes in the gate oxide layer, and thus decreased Vt and increased IDsat. Finally, C-V measurement is also carried out which further confirms the above analysis.

Improved LPCVD-SiNx/AlGaN/GaN MIS-HEMTs by using in-situ MOCVD-SiNx as an interface sacrificial layer

In this paper, the effects of a thin in-situ SiNx layer, grown by metal–organic chemical vapor deposition (MOCVD), on the performances of GaN-based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) with low-pressure chemical vapor deposition (LPCVD) SiNx gate dielectric were systematically investigated. We found that the MIS-HEMT with the in-situ SiNx as an interface sacrificial layer exhibits better DC electrical properties than that with the in-situ SiNx reserved as part of the gate dielectric. The results of second ion mass spectroscopy and electron spin resonance spectrum show that this in-situ SiNx is a Si-rich SiNx dielectric which can induce additional ≡Si0 and ≡Si- trap states by Si dangling bonds and affects significantly electron trapping and detrapping processes. Based on temperature-dependent gate current and frequency-dependent capacitance-voltage analyses, a trap model at the SiNx/AlGaN interface and in the in-situ SiNx bulk was proposed and well explains the performance discrepancies between the above mentioned two MIS-HMETs. In addition, positive bias temperature instability was carried out to further confirm the rationality of the proposed trap model. This work verifies that in-situ SiNx can be employed as a sacrificial layer for the fabrication of high performance LPCVD-SiNx/AlGaN/GaN MIS-HEMTs.

LaSiO x - and Al2O3-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration

Sequential 3-D stacking of multiple CMOS device tiers in a single fabrication flow requires the development of reliable high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula>/metal gate (HKMG) stacks at a reduced thermal budget (&#x003C;525 &#x00B0;C). The omission of the customary high-temperature gate-stack annealing results in excessive dielectric defect densities. We have recently demonstrated on MOS capacitors the insertion of &#x201C;defect decoupling&#x201D; layers&#x2013;LaSiO_<i>x</i> for nMOS and Al₂O₃ for pMOS&#x2013;at the interface between SiO₂ and HfO₂ as a promising approach to engineer the high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> band lineup and minimize charge trapping for improved bias-temperature-instability (BTI) reliability. In this article, we demonstrate this approach in planar transistors, which allows assessing the impact of defect decoupling on carrier mobility. First, a comparative study on the impact of LaSiO_<i>x</i> and Al₂O₃ insertion is performed, highlighting the different strategies for improving positive BTI (PBTI) and negative BTI (NBTI) reliability. Second, a comprehensive investigation on the effects of LaSiO_<i>x</i> and Al₂O₃ insertion is conducted with a focus on BTI reliability and channel carrier mobility: a lack of penalty (Al₂O₃) or even improved carrier mobility (LaSiO_<i>x</i>) is reported for the dipole-inserted gate stacks. Furthermore, we explore the simplified dual gate-stack integration for CMOS flow. A severe PBTI reliability penalty is observed if an Al₂O₃ layer (for hole trap decoupling) is deposited in the nMOS gate-stack, even if on top of the beneficial LaSiO_<i>x</i> (for electron trap decoupling). In contrast, the pMOS gate-stack is found to be more tolerant to the presence of a residual LaSiO_<i>x</i> layer on top of the beneficial Al₂O₃ layer, suggesting a viable strategy for the simplified dual gate-stack integration. Finally, the reliability improvement is validated also on a FinFET test vehicle.